1. Technical Field
The present invention relates to a thin film transistor (TFT) and, more particularly, to a method of fabricating a CMOS TFT, and a CMOS TFT fabricated using the method.
2. Related Art
A CMOS thin film transistor (TFT) is a device having a PMOS TFT and an NMOS TFT, and has the advantage of being capable of implementing various circuits and systems which are difficult to be implemented using only the NMOS TFT or the PMOS TFT.
In a method of fabricating a CMOS TFT, a substrate including a PMOS region and an NMOS region is provided, and then, a PMOS semiconductor layer and an NMOS semiconductor layer are formed on the PMOS region and the NMOS region using a first mask. A gate insulating layer is formed on the semiconductor layers. A gate conductive layer is deposited on the gate insulating layer, a photoresist pattern is formed on the gate conductive layer using a second mask, and the gate conductive layer is etched using the photoresist pattern as a mask, thereby forming a PMOS gate electrode overlying the PMOS semiconductor layer. At this point, a gate conductive layer shielded by the photoresist pattern remains in the NMOS region. Subsequently, by doping with P-type impurities in high concentration using the photoresist pattern and the PMOS gate electrode as masks, source and drain regions are formed in the PMOS semiconductor layer, and a channel region is defined between the source and drain regions.
The photoresist pattern is removed, and a new photoresist pattern is formed using a third mask. The gate conductive layer is etched to form an NMOS gate electrode overlying the NMOS semiconductor layer using the photoresist pattern as a mask. Next, by doping with N-type impurities in low concentration using the photoresist pattern and the NMOS gate electrode as masks, low concentration impurity regions are formed in the NMOS semiconductor layer, and a channel region is defined between the low concentration impurity regions.
The photoresist pattern is removed to form a photoresist pattern using a fourth mask. By doping with N-type impurities in high concentration using the photoresist pattern as a mask, high concentration impurity regions are formed in the NMOS semiconductor layer, and low concentration impurity regions remain at one side of the high concentration impurity regions to form a lightly doped drain (LDD) region.
The photoresist pattern is removed to expose the gate electrodes. An interlayer-insulating layer is formed on the exposed gate electrodes, and contact holes exposing portions of source and drain regions of the PMOS semiconductor layer and portions of the high concentration impurity region of the NMOS semiconductor layers are formed in the interlayer-insulating layer using a fifth mask. Subsequently, PMOS source and drain electrodes and NMOS source and drain electrodes respectively in contact with the exposed regions by the contact holes of the semiconductor layers through the contact holes are formed using a sixth mask.
In order to implement the CMOS TFT as described above, since both the PMOS TFT and the NMOS TFT have to be formed on one substrate, relatively many processes are required. In particular, as the LDD region is formed, in order to decrease leakage current and to solve a reliability problem, such as a hot carrier effect based on a scale-down of the NMOS TFT, the number of masks for implementing the CMOS TFT have to be increased. Therefore, as described above, the CMOS TFT including the NMOS TFT having the LDD region requires at least six masks.